コンピュータアーキテクチャ
担当教員
授業の到達目標及びテーマ
1. ISA (Instruction Set Architecture) 2. FPU (Floating Point Unit) 3. Cache and TLB (Translation Lookaside Buffer) 4. Multithreading CPU and Multi-core CPU 5. PS/2 Keyboard and Mouse Controller, VGA Controller, I2C and PCI Buses
授業の概要と方法
The contents of this course include performance issues, instruction set and instruction format, addressing mode, data presentation methods, advanced pipelining, static and dynamic instruction scheduling methods to exploit ILP (instruction level parallelism), FPU design, cache mapping methods and replacement algorithms, virtual memory, multi-core and multithreading techniques, storage systems, error correcting codes, interconnection networks, and multiprocessors. Quizzes will be done in the class. As a project, students will develop a simulator in C for the performance simulation, or design a pipelined CPU with FPU.
授業計画
| 回 | テーマ | 内容 |
|---|---|---|
| 1 | Instruction Set Architectures | Accumulator, stack, general-purpose register architectures |
| 2 | Pipelined CPU Design | Datapath, control unit, delayed branch, bypass, and pipeline stalls |
| 3 | Floating Point Adder Design | IEEE 754 single-precision and double-precision floating-point (FP) numbers and FP addition/subtruction operations |
| 4 | Pipelined CPU with FPU | Pipeline stages of IU, pipeline stages of FPU, and connection between IU and FPU |
| 5 | Instruction Level Parallelism | Instruction re-order, loop unrolling, superscalar, and VLIW |
| 6 | Memory and Cache Design | Gap between CPU and memory, cache mapping methods and replacement algorithms, and project: developping a cache simulator in C |
| 7 | Virtual Memory and TLB Design | Virtual space and real space, page, segmentation, memory manegement unit, and translation lookaside buffer |
| 8 | Trace Driven Simulation | Benchmarks, SPEC, trace driven simulation, and execution driven simulation |
| 9 | Multithreading CPU | Threads, thread selection algorithms, and multithreading CPU design issues |
| 10 | Multi-Core CPU | Multi-core, many-core, chip-multiprocessors, and Multi-core CPU design issues |
| 11 | Storage Systems | HDD and RAID |
| 12 | Error Correcting Codes (ECCs) | Parity check, Hamming-code, extended Hamming-code, and CRC |
| 13 | Input and Output Systems | I/O controllers, PS/2 keyboard and mouse, VGA controller, I2C and PCI buses |
| 14 | Interconnection Networks | 2D/3D Mesh/torus, hypercube, Dual-cube, Metacube, and RDN |
| 15 | Summary | Summary and review for final examination |
授業外に行うべき学習活動
Develop the cache simulator in C. Or design a pipelined CPU with FPU.
テキスト
John L. Hennessy and David A. Patterson, Computer Architecture: A Quantitative Approach, Fourth Edition, Morgan Kaufmann Publishers, Inc.
参考書
コンピュータの構成と設計 ― ハードウエアとソフトウエアのインタフェース〈上〉日経BP社 コンピュータの構成と設計 ― ハードウエアとソフトウエアのインタフェース〈下〉日経BP社 MIPS32 Architecture For Programmers (online PDF) See MIPS Run, Second Edition, Morgan Kaufmann Publishers, Inc.
成績評価基準
1. Class attendance: 15% 2. Quizzes: 25% 3. Project report: 30% 4. Final Examination: 30%
情報機器使用
Bring note-PC to the lecture
前年度の授業改善アンケートからの気づき
Students can select one project from two.