Verilog HDL によるCPU設計
担当教員
授業の到達目標及びテーマ
1. Verilog Hardware Description Languages (Verilog HDL) 2. Program with FPGA Board 3. Pipelined CPU Design with Verilog HDL
授業の概要と方法
This is an exercise-oriented course. The Altera Quartus II Web Edition CAD/CAE tool will be used for the logic synthesis and functional simulation. Students will use Quartus II and Verilog HDL to design a pipelined CPU and will write a technical report.
授業計画
| 回 | テーマ | 内容 |
|---|---|---|
| 1 | A sample Verilog HDL code and the usage of Quartus II | Structure of Verilog HDL module and synthesis with Quartus II Web Edition |
| 2 | Verilog HDL styles and combinational circuit design | Structural, dataflow, and behavioral styles, assign, if-else, case, always, and function |
| 3 | Registers and sequential circuit design | alway, clock posedge and negedge, blocking and non-blocking assignment |
| 4 | Using FPGA Board and clock design | Design a clock (minute : second) with 7-segment LED |
| 5 | MIPS instructions and ALU design | Design an ALU in Verilog HDL for MIPS instructions |
| 6 | Register file design with Verilog HDL behaviour style | Design a 32x32 register file for MIPS CPU |
| 7 | Data hazard, internal forwarding, and pipeline stall | Design the code for dealing with data hazards and control hazards |
| 8 | Control hazard and delayed branch | Design the code for dealing with data hazards and control hazards |
| 9 | The datapath design in Verilog HDL 1 | Design the pipeline registers in Verilog HDL |
| 10 | The datapath design in Verilog HDL 2 | Design the datapath in Verilog HDL |
| 11 | The control unit design in Verilog HDL 1 | Instrction decoder and control signals |
| 12 | The control unit design in Verilog HDL 2 | ID stage control unit design |
| 13 | Pipelined CPU synthesis and functional simulation | CPU plus memory and test code |
| 14 | Project checking and report submission | Check simulation waveform and submit report |
| 15 | Summary | Summary and review for final examination |
授業外に行うべき学習活動
1. Write the Verilog HDL codes for basic circuit, clock, and the pipelined CPU. 2. Write reports for each design
テキスト
Online materials
参考書
小林優, 入門Verilog HDL 記述, CQ 出版社 鈴木昌治著, ディジタル数値演算回路の実用設計, CQ 出版社
成績評価基準
1. Class Attendance: 15% 2. Homeworks: 10% 3. Clock Design and Report: 10% 4. Pipelined CPU Design and Report: 35% 5. Final Examination: 30%
情報機器使用
Bring note-PC to the lecture
前年度の授業改善アンケートからの気づき
More Verilog HDL examples were added.