コンピュータ構成と設計
担当教員
授業の到達目標及びテーマ
1. Multiple-cycle CPU 2. Pipelined CPU 3. Memory hierarchy 4. Input/output systems 5. Performance evaluation
授業の概要と方法
The contents of this course include MIPS instruction set architecture, assembly language programming, multiple-cycle CPU datapath and control unit design, pipelined CPU datapath and control unit design (internal forwarding, pipeline stall, and delayed branch), memory, cache, virtual memory, input and output systems, and computer performance evaluation. A CAD/CAE tool will be used for designing high-performance computers.
授業計画
| 回 | テーマ | 内容 |
|---|---|---|
| 1 | MIPS Instruction Set Architecture | MIPS instructions, types and formats, and exercise: translate program to binary format and check the execution results |
| 2 | Assembly Language Programming | Format of assembly language programs, iteration multiplication algorithm, and exercise: write a multiplication program with basic instructions |
| 3 | Sequential Logic Circuit Design | State transfer diagram, truth tables for next-state and output signals, and exercise: up/down counter design and simulation |
| 4 | Multiple-Cycle CPU Control Unit 1 | Truth tables for control signals, and exercise: control unit design |
| 5 | Multiple-Cycle CPU Control Unit 2 | Sequential logic circuit (control unit) and exercise: control unit design |
| 6 | Multiple-Cycle CPU Datapath | Connection of basic components, and exercise: datapath design |
| 7 | Multiple-Cycle CPU Computer | CPU and memory, and exercise: computer design and simulation |
| 8 | Pipelined CPU Control Unit 1 | Pipeline operations and exercise: control unit design |
| 9 | Pipelined CPU Control Unit 2 | Forwarding, pipeline stall, delayed branch, and exercise: control unit design |
| 10 | Pipelined CPU Datapath | Pipeline registers and exercise: datapath design |
| 11 | Pipelined CPU Computer | Operations of pipeline stages and exercise: computer design and simulation |
| 12 | Memory Hierarchy | RAM, ROM, SRAM, DRAM, cache, and MMU |
| 13 | Input/Output Systems | I/O bus, polling, interrupt, and DMA |
| 14 | Performance Evaluation | Clock frequency, CPI, performance, and MIPS (million instructions per second) |
| 15 | Summary | Summary and Review for Final Examination |
授業外に行うべき学習活動
1. Design and simulate circuits 2. Write reports for each design
テキスト
コンピュータの構成と設計 ― ハードウエアとソフトウエアのインタフェース〈上〉日経BP社 コンピュータの構成と設計 ― ハードウエアとソフトウエアのインタフェース〈下〉日経BP社
参考書
MIPS32 Architecture For Programmers (online PDF) See MIPS Run, Second Edition, Morgan Kaufmann Publishers, Inc.
成績評価基準
1. Class Attendance: 15% 2. Homework and Project Report: 40% 3. Final Examination: 45%
情報機器使用
Bring note-PC to the lecture
前年度の授業改善アンケートからの気づき
Increased design samples for easy understanding