コンピュータ構成と設計演習
担当教員
授業の到達目標及びテーマ
The emphasis of this course is on the basic issues of computer organization and computer design. Students will learn the principle and hardware implementation of the computer components and how to completely design a single-cycle CPU computer. Such contents are very important for the development of the embedded systems which are used everywhere. We will learn that no magic is required to make a computer work.
授業の概要と方法
The contents of this course include computer arithmetic algorithm and hardware implementation for integer numbers, MIPS instruction set architecture, multiplexer design, ALU design, register file design, single-cycle CPU datapath and control unit design, memory design, and single-cycle CPU computer design. Students will learn not only the design methods but also how to use the CAD/CAE design tool to implement the design and perform the functional simulation to verify the circuits.
授業計画
前期
| 回 | テーマ | 内容 |
|---|---|---|
| 1 | Combinational logic circuit design | AND, OR, NOT operations, truth table, logic equations, and exercise: 2_1 and 4_1 multiplexers design and simulation |
| 2 | Data representation and arithmetic algorithm 1 | Unsigned and 2's complement signed binary numbers, full adder, and exercise: full adder design and simulation |
| 3 | Data representation and arithmetic algorithm 2 | Addition and subtraction on 32-bit numbers, and exercise: 32-bit adder/subtracter design and simulation |
| 4 | The basic components of a computer system | Multiplexer, ALU, register file, ALU, control unit, memory, I/O interface, and exercise: 32-bit multiplexer design and simulation |
| 5 | Shift operations | Left shift, logic right shift, arithmetic right shift, and exercise: 32-bit barrel shifter design and simulation |
| 6 | Instruction set and arithmetic logic unit | MIPS instructions, ALU, and exercise: 32-bit ALU design and simulation |
| 7 | Register file | DFF, DFFE, registers, decoder, and exercise: 32x32-bit register file design and simulation |
| 8 | Control unit 1 | Instruction decoder, truth table for control signals and exercise: Single-cycle CPU control unit design |
| 9 | Control unit 2 | Logic equations, circuits, and exercise: Single-cycle CPU control unit design |
| 10 | Datapath 1 | Connection of basic components, and exercise: Single-cycle CPU datapath design |
| 11 | Datapath 2 | CPU datapath and exercise: Single-cycle CPU datapath design |
| 12 | Memory structure | Memory structure and read/write operations, and exercise: data memory and instruction memory design |
| 13 | Single-cycle CPU computer | CPU and memory, and exercise: single-cycle CPU computer design and simulation |
| 14 | Summary and report submission | Check simulation waveform and submit report |
| 15 |
授業外に行うべき学習活動
1. Design and simulate circuits if you did not finish them in the class
2. Write reports for each design
テキスト
コンピュータの構成と設計 ― ハードウエアとソフトウエアのインタフェース〈上〉日経BP社
コンピュータの構成と設計 ― ハードウエアとソフトウエアのインタフェース〈下〉日経BP社
参考書
MIPS32 Architecture For Programmers (online PDF)
成績評価基準
1. Class attendance: 15%
2. Project and report: 35%
3. Final examination: 50%