Advanced Networking and Computing - Yamin LI
年度
- 2016 年度版
Instructor
Goal and Theme
Most modern CPUs can exploit 3-level parallelism: (1) The CPUs can dispatch multiple instructions from an instruction stream in every clock cycle to exploit the instruction-level parallelism (ILP). (2) The CPUs can execute multiple threads simultaneously to exploit the thread-level parallelism (TLP). And (3) There are multiple cores in a single CPU chip so that it can execute multiple programs in parallel to exploit the job-level parallelism (Chip multiprocessors). To achieve high-performance in scientific computations, Wallace Tree, Goldschmidt algorithms and Newton-Raphson algorithms are used to speedup the operations of the multiplications, division, and square root. For computer/CPU design, the Verilog HDL (Hardware description language) is widely used by both academia and industry.
授業の到達目標
Through this lecture, students will learn how to design high-performance CPU in Verilog HDL. After finishing the lecture, students should become a professional in Verilog HDL and in CPU designs.
Abstract
The contents of the lecture include technology and performance evaluation, instruction architectures, pipelining, floating point adder design, Wallace Tree, Goldschmidt algorithms, Newton-Raphson algorithms, FPU/CPU design, multithreading/multicore CPU design, instruction scheduling and branch prediction, Scoreboard and Tomasulo algorithms, cache and TLB design, PS/2 Keyboard and mouse, VGA controller, and PCI Bus. In the last two classes, students will present their work related to this course.
Schedule
| 回 | テーマ | 内容 |
|---|---|---|
| 1 | Performance Evaluation | Introduction, computer performance evaluation, and Hardware Description Languages (HDLs) |
| 2 | Pipelining and Verilog HDL | Instruction architectures and pipelined CPU design in Vrilog HDL |
| 3 | Pricise Interrupt | Interrupts and exceptions, pricise interrupt in pipelined CPU |
| 4 | Floating Point Adder Design | IEEE 754 floating-point formats, FPU addition and subtraction |
| 5 | Wallace Tree | Multiplication and Wallace Tree Circuit |
| 6 | Goldschmidt Algorithms | Goldschmidt divison and square root algorithms |
| 7 | Newton-Raphson Algorithms | Newton-Raphson divison and square root algorithms |
| 8 | FPU/CPU Design | Advanced CPU/FPU design |
| 9 | Cache and TLB | Memory hierarchy, cache, MMU, TLB, and CPU design with caches and TLBs |
| 10 | Multithreading CPU Design | Threads and multithreading CPU Design |
| 11 | Multicore CPU Design | Cache coherency protocols and Multicore CPU Design |
| 12 | Input and Output Systems | PS/2 Keyboard and mouse, VGA controller, and PCI Bus |
| 13 | Supercomputers | High-performancs computers and interconnection network |
| 14 | Presentations | Present your theme |
| 15 | Presentations | Present your theme |
授業時間外の学習 (準備学習・復習・宿題等)
Write Verilog HDL codes for CPU design or develop interconnection networks, and prepare presentation slides
Materials
Online materials
References
1. Computer Architecture: A Quantitative Approach, Fifth Edition, John L. Hennessy and David A. Patterson, Morgan Kaufmann Publishers, Inc. 2011.
2. Computer Principles and Design in Verilog HDL, Yamin Li, John Wiley & Sons, ISBN 978-1-118-84109-9, 2015.
Evaluation Method
Based on attendance and presentations
情報機器使用
Bring note-PC to the lecture
学生の意見 (授業改善アンケート等) からの気づき
None